Advanced dielectric film growth technique for next generation power devices
Toward high performance SiC devices by reducing defects at SiC/dielectric interface
Graduate School of Engineering / Faculty of Engineering
High performance power devices, which are used for high current, high voltage and high frequency applications, offer the potential for large energy saving. In particular, silicon carbide (SiC) devices offer the potential for lower energy loss than conventional silicon devices. However, SiC transistors suffer from high resistance and low reliability, mainly due to defects formed at the interface between SiC gate dielectric film. Such defects, caused by impurities and atomic excess or deficiency at the interface, need to be reduced to improve the performance.
The research group of Associate Professor Koji Kita at the University of Tokyo Graduate School of Engineering, found that the density of interface defects is significantly reduced by employing reaction conditions where the byproduct carbon is ejected as carbon monoxide when creating the gate dielectric film. The group achieved the lowest defect density in a MOS (metal-oxide-semiconductor) test structure employing these conditions.
This technique provides a high quality SiC interface without any extra processes such as addition of nitrogen-containing gases, assuring the easy industrial application of this method. This technique is expected to improve the performance and accelerate the spread of SiC power devices, contributing to energy saving in a variety of applications, including electric power transmission, electric vehicles, and factory machines.
Richard Heihachiro Kikuchi and Koji Kita,
“Fabrication of SiO2/4H-SiC (0001) Interface with Nearly-Ideal Capacitance-Voltage Characteristics by Thermal Oxidation”,
Applied Physics Letters Online Edition: 2014/07/25 (Japan time), doi: 10.1063/1.4891166.
Article link (Publication, UTokyo Repository)