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New tunneling field effect transistors operating at extremely-low power consumption

Utilizing a structure combining strained-Silicon with Germanium

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Graduate School of Engineering / Faculty of Engineering
2015/01/13

The research group of Professor Shinichi Takagi and Associate Professor Mitsuru Takenaka in the University of Tokyo Graduate School of Engineering Department of Electrical Engineering and Information Systems have succeeded in development of a new tunnel field effect transistor (tunnel FET) able to operate using an extremely low supply voltage.

Cross sectional structure of tunnel FETs, reported in this study. Here, heavily-doped p-type Ge (Germanium) is formed on strained-Si channels and the Aluminum Oxide (Al2O3) gate insulator and Tantalum (Ta) gate electrode are formed on strained-Si channels with highly-doped n-type drain regions. Nickel (Ni) contact electrodes are deposited on the Ge sources. These electrodes have aluminum contact electrodes. Buried oxides are formed between Si substrates and strained-Si channels. Application of gate voltage makes the surface layer of strained-Si with n-type high-carrier concentration, allowing to tunneling current in this surface region.

© 2015 M.-S. Kim, Y. Wakabayashi, R. Nakane, M. Yokoyama, M. Takenaka and S. Takagi.Cross sectional structure of tunnel FETs, reported in this study. Here, heavily-doped p-type Ge (Germanium) is formed on strained-Si channels and the Aluminum Oxide (Al2O3) gate insulator and Tantalum (Ta) gate electrode are formed on strained-Si channels with highly-doped n-type drain regions. Nickel (Ni) contact electrodes are deposited on the Ge sources. These electrodes have aluminum contact electrodes. Buried oxides are formed between Si substrates and strained-Si channels. Application of gate voltage makes the surface layer of strained-Si with n-type high-carrier concentration, allowing to tunneling current in this surface region.

The increase in power consumption of IT devices is a matter of major international concern. There is intense competition to develop very-low power consumption devices operating on different principles to conventional MOS (metal oxide semiconductor) transistors.

In this study, research group created a novel tunnel field effect transistor with junctions composed of Germanium sources and strained-Silicon channels and having almost the same device structure as conventional MOS transistors. It has been demonstrated that this MOSFET exhibits world-record high ratio of on-current to off-current with steep current change on a minute change in gate voltage. This device opens the way to realizing integrated circuits operating at a supply voltage of 0.3 V and lower, potentially enabling a significant reduction in power consumption by IT devices and new applications including the development of batteryless circuits.

This research was carried out under the Japan Science and Technology Agency (JST) CREST Research Project “Innovative nano-electronics through interdisciplinary collaboration among material, device and system layers” (Development of Tunneling MOSFET Technologies for Integrated Circuits with Ultra-Low Power Consumption).

Press release

Paper

M.-S. Kim, Y. Wakabayashi, R. Nakane, M. Yokoyama, M. Takenaka and S. Takagi,
“High Ion/Ioff Ge-source ultrathin body strained-SOI Tunnel FETs – impact of channel strain, MOS interfaces and back gate on the electrical properties”,
Tech. Dig. International Electron Device Meeting (IEDM) 2014: p. 331-334.

Links

Graduate School of Engineering

Department of Electrical Engineering and Information Systems (EEIS), Graduate School of Engineering

Takagi and Takenaka Group, Department of Electrical Engineering and Information Systems (EEIS), Graduate School of Engineering

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