Faster, longer, better New Solid-State Drive reads faster, lasts longer, and reduces errors

February 24, 2012

A research team lead by Associate Professor Ken Takeuchi from the University of Tokyo’s Graduate School of Engineering, Department of Electrical Engineering and Information Systems, and Professor Tadahiro Kuroda and Associate Professor Hitoshi Ishiguro of Keio University’s Graduate School of Science and Technology, have developed a form of non-contact solid state drive (SSD) memory that revolutionizes the three core technologies of SSD memory: high-speed access, wireless communications, and wireless charging. This research was supported by the Japan Science and Technology Agency (JST) program for Use-Inspired Fundamental Research

The research will be announced at the International Solid-State Circuits Conference (ISSCC 2012) to be held in San Francisco from 19 to 23 February 2012. The ISSCC is the authoritative forum for research in Solid State Circuits. It is a significant achievement that three papers have been adopted from the same group this year.

The research group has developed a 76%-reduced-error Solid-State Drive (SSD) with an extended lifetime over 10 times that of current SSDs. This error-prediction low-density parity-check (LDPC) error correcting code (ECC) scheme achieves both high reliability as well as a 7-times faster read. A new data retention time estimation scheme has also been created. Errors are most effectively corrected by calibrating memory data based on threshold voltage (VTH), inter-cell coupling, write/erase cycles, and data retention time. This error recovery scheme is also expected to reduce program disturb error by 76% and data retention error by 56%.

The integration of these results will make possible wireless SSD memory of capacities greater than 128Gbit, which if used in data centers could result in a ten-fold increase in processing speed and a 50 percent cut in power consumption compared to conventional hard disks. Products based on this technology are expected to have a significant impact on the one trillion yen global market for memory modules. In the future, this technology will be key to achieving battery-free large-capacity memory cards.

Press release (Japanese)

Paper (presented at ISSCC 2012)

S. Tanakamaru, Y. Yanagihara, K. Takeuchi,
“Over 10-times Extended Lifetime, 76% Reduced Error Solid-State Drives (SSDs) with Error Prediction LDPC Architecture and Error Recovery Scheme,”

Research group members at Keio University

W-J. Yun, S. Nakano, W. Mizuhara, A. Ko (Keio University),
“A 7Gb/s/Link Non-Contact Memory Module for Multi-Drop Bus System Using Energy-Equipartitioned Coupled Transmission Line”

R. Shinoda, K. Tomita, Y. Hasegawa, H. Ishikuro (Keio University),
“Voltage-Boosting Wireless Power Delivery System With Fast Load Tracker by ΔΣ-Modulated Sub-Harmonic Resonant Switching”


Takeuchi Lab

IEEE International Solid-State Circuits Conference (ISSCC)

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